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I blamed PCIe topology for my 4-GPU tensor-parallel collapse. It was Windows' display driver. A $100 card and TCC mode turned 9.5 t/s into 28 (4x A4000, llama.cpp, verified)

This story is from 2026-09-06. It is preserved in the archive; the latest stories are on the live feed.

TL;DR: Four A4000s in a dual-Xeon box ran 4-way tensor parallel 2.4 to 4.8x SLOWER than two cards. I publicly blamed lanes, root complexes, and the inter-socket link. Wrong. WDDM (the Windows display driver model) silently denies GPU peer-to-peer access, so every cross-card transfer staged through…

Read the full story at r/LocalLLM ↗

Timeline · 2 reports

  1. 2026-09-08 08:22 · r/LocalLLaMA
    I made a custom llama.cpp build optimized for 7900xtx (one or two). for qwen 3.8 next and 27B. includes optimizations for PciE x4 and tensor parallel. read inside! (no AI slop)
  2. 2026-09-06 16:55 · r/LocalLLM
    I blamed PCIe topology for my 4-GPU tensor-parallel collapse. It was Windows' display driver. A $100 card and TCC mode turned 9.5 t/s into 28 (4x A4000, llama.cpp, verified)

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