Robustness of LLM-Generated SystemVerilog Assertions to Semantics-Preserving RTL Transformations
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arXiv:2609.05658v1 Announce Type: new Abstract: Large language models (LLMs) are increasingly being explored for automating SystemVerilog Assertion (SVA) generation, yet most evaluations report correctness on a single syntactic representation of an input. Such point accuracy does not reveal whether…
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- 2026-09-09 04:00 · arXiv cs.LG
Robustness of LLM-Generated SystemVerilog Assertions to Semantics-Preserving RTL Transformations